Integrated circuit design is constantly being scaled down in pursuit of faster circuit operation and lower power consumption. Scaled dimensions in a circuit design generally requires attendant changes in fabrication processing.
A basic building block of integrated circuits is the thin film transistor (TFT). As is known in the art, the transistor typically includes a gate electrode separated from a semiconductor layer or substrate by a thin gate dielectric material. Although a common acronym for state-of-the-art transistors is MOS, for metal-oxide-silicon, the material of choice for the gate electrode has long been silicon rather than metal. Among other advantages, silicon gate electrodes are able to withstand high temperature processes and enable self-aligned doping processes used for completing the transistor, thus saving expensive masking steps.
Accordingly, conventional gate electrodes are formed of polysilicon doped with conductivity-enhancing impurities, such as arsenic, phosphorus or boron. Silicon can be deposited by CVD with in situ doping by flowing a dopant source gas (e.g., arsine, phosphine, diborane, etc.) concurrently with a silicon source gas (e.g. silane).
Recently, interest has been drawn to the possibility of doping silicon electrodes with germanium, thereby reducing the electrical work function of the transistor gate electrode. Accordingly, a reduced voltage is needed to operate the circuit, consequently generating less heat. Moreover, a silicon germanium gate electrode remains compatible with surrounding materials and current integrated circuit fabrication processes. Proposals for flowing silicon germanium layers include in situ doping of a silicon layer by forming germane (GeH4) along with silane (SiH4) in a chemical vapor deposition (CVD) process.
While in situ doped CVD processes have been found to be effective in producing silicon germanium, the addition of germane to the silane flow has been found to significantly increase incubation or nucleation times over dielectric materials, particularly oxides such as silicon dioxide and some of the high-k materials discussed below. Similarly slow nucleation over dielectric materials occurs when chemical vapor depositing polysilicon, and is particularly acute when in situ flowing other dopant source gases.
Slow nucleation entails higher overall deposition times, lower throughput and consequently greater fabrication costs. The semiconductor industry is very sensitive to fabrication costs. Accordingly, any increase in wafer throughput, at any stage of processing, translates to reduced production costs and higher margins. Furthermore, the initial poor nucleation can lead to poor quality of the resultant layer, including problems with stoichiometry, density, surface planarity, etc.
One way in which SiGe or other in situ doped silicon deposition has been hastened is by the first formation of a nucleation layer, typically of polysilicon, over the gate dielectric, followed by poly-SiGe deposition. However, this additional step complicates the process flow and requires adjustment of the doping concentrations at the dielectric-electrode interface to ensure the desired work function for the transistor.
Another area in which process control is particularly critical is the fabrication of transistor gate dielectrics. In the pursuit of ever faster and more efficient circuits, semiconductor designs are continually scaled down with each product generation. Transistor switching time plays a large role in the pursuit of faster circuit operation. Switching time, in turn, can be reduced by reducing the channel length of the transistors. In order to realize maximum improvements in transistor performance, vertical dimensions should be scaled along with horizontal dimensions. Accordingly, effective gate dielectric thickness, junction depth, etc. will all decrease with future generation integrated circuits.
Conventional gate dielectrics are formed of high quality silicon dioxide and are typically referred to as “gate oxide” layers. Ultra thin gate oxides (e.g., less than 5 nm), however, have been found to exhibit high defect densities, including pinholes, charge trapping states, and susceptibility to hot carrier injection effects. Such high defect densities lead to leakage currents through the gate dielectric and rapid device breakdown unacceptable for circuit designs with less than 0.25 μm gate spacing, i.e., sub-quarter-micron technology.
While care under laboratory conditions can be used to control defect densities, such control has been difficult to achieve under commercial volume fabrication conditions. Moreover, even if the integrity of the oxide is perfectly maintained, quantum-mechanical effects set fundamental limits on the scaling of gate oxide. At high fields, direct tunneling dominates over Fowler-Nordheim tunneling, and largely determines oxide scaling limits. These scaling limits have been estimated at about 2 nm for logic circuits, and about 3 nm for more leakage-sensitive memory arrays in dynamic random access memory (DRAM) circuits. See, e.g., Hu et al., “Thin Gate Oxides Promise High Reliability,” SEMICONDUCTOR INTERNATIONAL (July 1998), pp. 215–222.
Theoretically, incorporating materials of higher dielectric constant into the gate dielectric opens the door to further device scaling. Due to higher dielectric constant, many materials can exhibit the same capacitance as a thinner silicon dioxide layer, such that a lower equivalent oxide thickness can be achieved without tunnel-limited behavior. Silicon nitride (Si3N4), for example, has a higher dielectric constant than SiO2 and also demonstrates good diffusion barrier properties, resisting boron penetration. More exotic materials with even higher dielectric constants, including aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), barium strontium titanate (BST), strontium bismuth tantalate (SBT), tantalum oxide (Ta2O5), etc., are also being investigated to allow further device scaling.
Similar high quality, thin dielectric layers are desirable in other contexts of integrated circuit fabrication. Integrated capacitors in memory arrays must exhibit a certain minimum capacitance for proper data storage and retrieval. Some efforts to increase capacitance for a given memory cell space have focused on the use of materials characterized by high dielectric constants (high k materials), such as those listed above.
As noted above, it is often difficult to deposit electrode materials, such as polysilicon, amorphous silicon, and particularly doped silicon or silicon germanium alloys, over conventional silicon oxides as well as many of the high k materials currently under investigation. Many other types of materials and deposition techniques in integrated circuit fabrication face issues that depend upon the substrate surface upon which the material is to be deposited.
Intermediate layers are often deposited prior to deposition of the desired functional layer for a variety of remedial reasons, including otherwise poor adhesion, nucleation, electrical interface properties, diffusion, etc. Such intermediate layers add to the complexity and cost of fabrication, and can also occupy valuable space within high aspect ratio features, such as contact vias or folded structures for high surface area capacitors. In some contexts, like gate dielectrics and capacitor dielectrics, additional layers increase the overall dielectric thickness and reduce the effectiveness of the layer, contrary to the trend for scaling down integrated circuits.
Accordingly, a need exists for improving the speed, efficiency, quality and uniformity of depositing layers in semiconductor fabrication.